Architecture Selection and Verification

• Architecture class, processor type, communication type, and topology
• Physical decomposition (processor element, ASIC,FPGA)
• Partition and map architecture independent flow graphs
• Generate simulators and iteratively refine and simulate to optimize
• Begin non-DFG/CFG software design
• Populate trade-off matrix for selection of one or more architecture candidates

• Evaluate existing models and develop new ones
• Autocode from command and data flow graphs
• Simulate to account for OS, graph management, and scheduling overhead
• Develop hierarchical verification plan
• Hierarchically co-simulate hardware and software
• Update trade-off analysis and select the candidate architecture