VHDL Extensions - Honeywell Tech. Center

• Reduce design cost/time through hierarchical model based prototyping
• Develop methodology for common language usage - VHDL
• Improve interoperability of models by developing interface conventions where most needed
• Promote model based design by increasing the availability of needed modeling libraries with perpetuation through commercialization path

BENEFITS

• Model re-use cuts system development time/cost > 50%
• Models from a variety of sources will be useful to a greater number of designers
• Path to commercialization
• Commercial tools available 4Q96
• Leverage previous developments by enhancing existing PML (Performance Model Library)