VHDL Model Taxonomy Working Group

• Develop uniform terminology for model types
• Develop consistent taxonomy for describing model's information content
• Support model selection, design capture, model usage, design testing, and hardware/software codesign
• Generate and promulgate consensus through publication and introduction to parallel working committees

BENEFITS

• Unambiguous communication and model classification supports greater model reuse
• Forms basis for interoperability conventions

• RASSP Educator/Facilitator and VHDL BAA activities
  • University of Virginia
  • Mississippi State University
  • Georgia Tech.
  • Intermetrics
  • University of Cincinnati