RASSP DFT Methodology and TSD Implementation

• Create DFT component models/procedures which are installable in project designs across design, manufacturing, and field phases
• Contribute to architectures selection process as Figure Of Merit entry
• Create reusable elements
  • Procedure Templates
  • VHDL Models
  • Test Procedures
  • Test Vector Set

BENEFITS

• Eliminate need for redevelopment of design, manufacturing, and field elements which span a variety of projects
• Shorten installation time of DFT for a project
• Reduction of actual test time and cost for a project

• Requirements consolidation procedure fully developed and verified complete
  • Requirements templates (including completed templates as appropriate)
  • Consolidation procedure
• VHDL models for critical DFT components to implement 1149.1 and 1149.5 class test busses generated and validated
  • JTAG buffers
  • Test bus controllers
  • Test vector sets
• Template for test equipment selection based on component class and project phase complete

• Benchmark 3 Shadow Program used to develop reusable library elements