VHDL Interface: Behavioral Model Generator - Synopsys/LMG

• Automated VHDL model development for Complex Bus Interface models, simple full functional models
• Reduced model development cycle time and cost
• Graphical user interface driven
• Promote uniform modeling style

  BENEFITS
  

  • Lower cost to generate models; 10X productivity improvement
  • Greater model availability
  • Standard style promotes model interoperability/reusability among internal/external groups

• Delivered Version 1 - 11/95
• Evaluation - 6/96 completed;
  • ATL supplied feedback to Synopsys
  • "Model Maker" product now available from Synopsys LMG

• VHDL taxonomy
• DARPA VHDL BAA activities at University of Virginia, Georgia Tech, University of Mississippi, Honeywell Technology Center, Intermetrices, Univerisity of Cincinnati