Architecture Tradeoff Tool (NetSyn) - JRS (BDTI)


TECHNICAL OBJECTIVES
  • Provide tool to facilitate rapid architecture tradeoffs
  • Couple capability with other tools to support iterative, hierarchical tradeoffs

BENEFITS

  • Tradeoffs driven from data flow graph
  • Integrated with visualization ADVT) tools to support graphical architecture definition
  • Automatic or manual mapping of graphs to architecture
  • VHDL performance simulation provides early sizing verification
  • Flexible import/export to other tools improves design flow
  • Size, weight and power estimates provide initial tradeoff parameters

RESULTS
Basic tool enhancements, integrations(RDD-100, Fidelity, PRICE, Autocode) - Complete
Final enhancements - Complete
VHDL export, PGM import (from SPW) - Discontinued
Visualization tool integration (ADVT) - Complete
 RELATED EFFORTS
  • Common API for multi-tool input to NetSyn is being developed
  • JRS acquired by Motorola in 1996
    • Pursuing internal developments/enhancements
RASSP-developed architecture tradeoff capability
enables rapid selection/sizing of optimal solutions

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WBS Element No.: 1.2.3.4, 1.2.3.5, 1.2.3.6, 1.2.3.17, 1.2.3.18 and 1.2.3.19
Point of Contact: Deborah Runner (714) 704 - 1670
or e-mail debbie@jrs.com

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