Integrated Performance Simulation - JRS/Omniview/HTC/MCCI/LMC

TECHNICAL OBJECTIVES
  • Provide perforance simulation which reflects OS, Autocoding and Run-Time System

BENEFITS

RESULTS
Initiated in - 1Q96
NetSyn/PMW/ADVT integration - Complete
Autocoding integration - 1Q97
ADVT/RTSintegration - 2Q97
PGMSim definition and requirements - Complete
Effort stopped, redirected to development of RASSP integrated architecture toolset (new quad)   
 BENEFITS
  • VHDL performance modeling development
  • PMW development and VHDL Library commercialization under RASSP BAA
  • MCCI autocoding development

Architecture selection and verification are tightly coupled through multiple
levels of performance simulation with common visualization

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WBS Element No.: 1.2.3.1
Point of Contact: Bernie Schaming (609) 338 - 4219
or e-mail wschamin@atl.lmco.com

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