SYSTEM LEVEL SIMULATION
- Function and timing simulation of required processing
ARCHITECTURE LEVEL SIMULATION
- Performance simulation to evaluate partitioning and mapping on candidate architectures
- Functional simulation to validate autocode
- Performance re-simulation using autocode timing
- Hierarchical functional and performance simulation for final verification
DETAILED DESIGN SIMULATION
- Low level simulation (RTL and below) prior to design release
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BENEFITS
- Enables mutual influence of both hardware and software early in design
- Provides continual verification which improves quality
- Automation of codesign early in the process and tool interoperability enables evaluation of larger design space
- Co-verification throughout the virtual prototyping process reduces integration and test time
- Integrated architecture toolset supported by commercial tool suppliers
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