RASSP Hardware/Software Codesign Process

• Define and instantiate a new process for selection and verification of architectures based on hardware/software codesign
  • Process must allow exploiting the use of COTS DSP solutions
  • Process must support the RASSP cycle time, cost and quality improvement goals
• Provide autocoding capability for both signal processing application and control software
• Enhance/integrate tools to support new process
  

• New architecture tradeoff tools developed
• New tools and tool extensions developed for SPW , BONeS, NetSyn, MCCI (Autocode Toolset), HSIM, PMW, RDD-100, SPEAR, MATLAB, and PGM tools
• 10X productivity improvement demonstrated using DSP SW autocoding for algorithms
• Control software autocoding demonstrated
  • Integration to DFG autocode - 4Q97
• Partial tool suite integration - 4Q96/Final 3Q97

• Provides direct coupling with algorithm tools used in Systems process
• Formalizes tradeoff process
• Hardware and software no longer independent
• Performance simulation drives architecture and software decisions
• Autocoding of signal processing and control software
• Run-Time System and debugger support autocode approach