RASSP Hardware/Software Codesign Process

Architecture Selection and Verification Process

TECHNICAL OBJECTIVES
  • Define and instantiate a new process for selection and verification of architectures based on hardware/software codesign
    • Process must allow exploiting the use of COTS DSP solutions
    • Process must support the RASSP cycle time, cost and quality improvement goals
  • Provide autocoding capability for both signal processing application and control software
  • Enhance/integrate tools to support new process
RESULTS
BENEFITS
  • Provides direct coupling with algorithm tools used in Systems process
  • Formalizes tradeoff process
  • Hardware and software no longer independent
  • Performance simulation drives architecture and software decisions
  • Autocoding of signal processing and control software
  • Run-Time System and debugger support autocode approach

The RASSP Architecture process provides a seamless path from
algorithm specification to autocoded software for target processors

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WBS Element No.: 1.2.3 and 1.2.5
Point of Contact: Bernie Schaming (609) 338 - 4219
or e-mail wschamin@atl.lmco.com

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